The present invention relates to test structures generally and, more particularly, to a test structure for simultaneous switching output (SSO) analysis.
Simultaneous Switching Noise (i.e., SSN or Delta I) is defined as the noise induced by the switching lines (or aggressor lines) on unswitching or quiet lines (i.e., victim lines) at a receiver-end. To ensure that no false pulses are caused as a result of high simultaneous switching output (SSO) noise, conventional designs adhere to the constraint that SSN is always below the noise margins of the receiver. The results can be used as a reference throughout the design phase of the chip, and should be re-examined whenever the user-specified conditions and structures are modified.
It would be desirable to implement a test structure for ensuring correlation between simulations and actual production silicon.
The present invention concerns an apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a plurality of intermediate signals from a data signal. Each of the intermediate signals may be switchable between (i) a common delay and (ii) one of a plurality of staggered delays determined by a stagger signal. The a second circuit may be configured to generate a plurality of first drive signals by gating the intermediate signals with a plurality of enable signals. The third circuit may be configured to generate a plurality of first output signals at a transmit interface of a chip by buffering the first drive signals.
The objects, features and advantages of the present invention include providing a test structures for simultaneous switching output (SSO) analysis that may (i) provide a flexible modular design which may be used for any type of technology, buffer, and/or package with little or no additional design overhead, (ii) provide extendability where the number of buffers in each SSO group can be easily extended to higher numbers without significant changes to the controller or any other circuits involved and where the number of buffers may be extended by adding more I/O buffers and increasing the capacity of the demultiplexer, (iii) provide simplicity by implementing (a) internal logic in a regular pattern that is easy to implement, (b) a design where not all lines from the output buffers of the transmitting chip may be connected to the receiving chip, and (c) a sample of two switching lines that may be adequate to perform Excess Incremental Delay (EID) and noise margin measurements to simplify the board design process and reduce board size, (iv) implement controllability since most of the variables (e.g., buffer type, number of switching buffers, frequency and voltage supply) may be controlled by the test engineer which enables the user to investigate the effects of these parameters on SSO noise easily, (v) implement two quiet lines in each SSO group to offer a simple and straight forward measurement of ground bounce and power droop, (vi) terminate most of the switching lines appropriately, close to the transmitting chip to reduce the complexity of the board design and save real estate on board, (vii) switch one line per buffer type to measure the noise margin of the receiver where the same line has a switch to enable the selection of a transmitted signal (from transmitting chip) or an external ramp or DC signal to be applied to the receiver, (viii) provide test or measurement points on the quiet lines that are placed as close as possible to the receiver pin such that the noise measured on these test points would have the same level at the input of the receiver, (ix) be applied to the test point on the reference line, where Excess Incremental Delay (EID) is measure for varying numbers of simultaneously switching buffers, and/or (x) implement two or more packages that can be used with the same design such that their parasitics can be easily evaluated and their performance compared.